MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

4–1

REV 1

8/97

Triple PECL to ECL Translator

The MC100LVEL/EL91 is a triple PECL to ECL translator. The

MC100LVEL91 receives low voltage PECL signals and translates them to

differential ECL output signals. The MC100EL91 receives standard

voltage PECL signals and translates them to differential ECL output

signals.

A VBB output is provided for interfacing with single ended PECL signals

at the input. If a single ended input is to be used the VBB output should be

connected to the D input. The active signal would then drive the D input.

When used the VBB output should be bypassed to ground via a 0.01µF

capacitor. The VBB output is designed to act as the switching reference

for the EL/LVEL91 under single ended input switching conditions, as a

result this pin can only source/sink up to 0.5mA of current.

To accomplish the level translation the EL/LVEL91 requires three

power rails. The VCC supply should be connected to the positive supply,

and the VEE pin should be connected to the negative power supply. The

GND pins are connected to the system ground plain. Both VEE and VCC

should be bypassed to ground via 0.01

µF capacitors.

Under open input conditions, the D input will be biased at VCC/2 and

the D input will be pulled to GND. This condition will force the Q output to

a low, ensuring stability.

ECL

ECL

ECL

D2

D1

Figure 1. 20–Lead Pinout (Top View) and Logic Diagram

D1

17

18

16

15

14

13

12

4

3

5678

9

Q0

11

10

Q1

Q1

Q2

Q2

VCC

D0

19

20

2

1

VCC

Q0

D0

D2

VCC

VEE

GND

GND

PECL

PECL

PECL

MC100LVEL91

MC100EL91

DW SUFFIX

20–LEAD PLASTIC SOIC WIDE PACKAGE

CASE 751D–04

PIN NAMES

Function

PECL/LVPECL Inputs

ECL/LVECL Outputs

PECL Reference Voltage Output

Pins

Dn

Qn

PECL_VBB