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FIN1049 Scheda tecnica(PDF) 5 Page - Fairchild Semiconductor |
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FIN1049 Scheda tecnica(HTML) 5 Page - Fairchild Semiconductor |
5 / 10 page 5 www.fairchildsemi.com Required Specifications 1. Human Body Model ESD and Machine Model ESD should be measured using MIL-STD-883C method 3015.7 standard. 2. Latch-up immunity should be tested to the EIA/JEDEC Standard Number 78 (EIA/JESD78). Note: CL = 15pF, includes all probe and jig capacitances FIGURE 1. Differential Receiver Voltage Definitions Test Circuit TABLE 1. Receiver Minimum and Maximum Input Threshold Test Voltages Note: RL = 100Ω FIGURE 2. LVDS Output Circuit for DC Test Applied Voltages (V) Resulting Differential Input Resulting Common Voltage (mV) Mode Input Voltage (V) VIA VIB VID VIC 1.25 1.15 100 1.2 1.15 1.25 −100 1.2 VCC VCC - 0.1 100 VCC - 0.05 VCC - 0.1 VCC −100 VCC - 0.05 0.1 0.0 100 0.05 0.0 0.1 −100 0.05 1.75 0.65 1100 1.2 0.65 1.75 −1100 1.2 VCC VCC - 1.1 1100 VCC - 0.55 VCC - 1.1 VCC −1100 VCC - 0.55 1.1 0.0 1100 0.55 0.0 1.1 −1100 0.55 |
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