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J112 Scheda tecnica(PDF) 2 Page - ON Semiconductor |
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J112 Scheda tecnica(HTML) 2 Page - ON Semiconductor |
2 / 4 page J112 2 Motorola Small–Signal Transistors, FETs and Diodes Device Data TYPICAL SWITCHING CHARACTERISTICS 1000 1.0 2.0 5.0 10 20 50 100 200 500 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 ID, DRAIN CURRENT (mA) Figure 1. Turn–On Delay Time RK = 0 TJ = 25°C VGS(off) = 7.0 V RK = RD′ 1000 1.0 2.0 5.0 10 20 50 100 200 500 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 ID, DRAIN CURRENT (mA) Figure 2. Rise Time RK = RD′ RK = 0 TJ = 25°C VGS(off) = 7.0 V 1000 1.0 2.0 5.0 10 20 50 100 200 500 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 ID, DRAIN CURRENT (mA) Figure 3. Turn–Off Delay Time RK = RD′ RK = 0 TJ = 25°C VGS(off) = 7.0 V 1000 1.0 2.0 5.0 10 20 50 100 200 500 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 ID, DRAIN CURRENT (mA) Figure 4. Fall Time RK = RD′ RK = 0 TJ = 25°C VGS(off) = 7.0 V NOTE 1 The switching characteristics shown above were measured using a test circuit similar to Figure 5. At the beginning of the switching interval, the gate voltage is at Gate Supply Voltage (–VGG). The Drain–Source Voltage (VDS) is slightly lower than Drain Supply Voltage (VDD) due to the voltage divider. Thus Reverse Transfer Capacitance (Crss) or Gate–Drain Capacitance (Cgd) is charged to VGG + VDS. During the turn–on interval, Gate–Source Capacitance (Cgs) discharges through the series combination of RGen and RK. Cgd must discharge to VDS(on) through RG and RK in series with the parallel combination of effective load impedance (R ′D) and Drain–Source Resistance (rds). During the turn–off, this charge flow is reversed. Predicting turn–on time is somewhat difficult as the channel resistance rds is a function of the gate–source voltage. While Cgs discharges, VGS approaches zero and rds decreases. Since Cgd discharges through rds, turn–on time is non–linear. During turn–off, the situation is reversed with rds increasing as Cgd charges. The above switching curves show two impedance conditions; 1) RK is equal to RD, which simulates the switching behavior of cascaded stages where the driving source impedance is normally the load impedance of the previous stage, and 2) RK = 0 (low impedance) the driving source impedance is that of the generator. RGEN 50 Ω VGEN INPUT RK 50 Ω RGG VGG 50 Ω OUTPUT RD +VDD RT SET VDS(off) = 10 V INPUT PULSE tr tf PULSE WIDTH DUTY CYCLE ≤ 0.25 ns ≤ 0.5 ns = 2.0 µs ≤ 2.0% RGG & RK RD + RD(RT ) 50) RD ) RT ) 50 Figure 5. Switching Time Test Circuit |
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