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GD25D10CPFG Datasheet(Scheda tecnica) 10 Page - GigaDevice Semiconductor (Beijing) Inc.

Numero della parte GD25D10CPFG
Dettagli  3.3V Uniform Sector Standard and Dual Serial Flash
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Produttore  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
Homepage  http://www.gigadevice.com/
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3.3V Uniform Sector
Standard and Dual Serial Flash
GD25D10C/05C
10
6. STATUS REGISTER
S7
S6
S5
S4
S3
S2
S1
S0
SRP
Reserved
Reserved
BP2
BP1
BP0
WEL
WIP
The status and control bits of the Status Register are as follows:
WIP bit.
The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress.
When WIP bit is set to 1, it means the device is busy in program/erase/write status register progress. when WIP bit is cleared
to 0, it means the device is not in program/erase/write status register progress. The default value of WIP is 0.
WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal
Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or
Erase command is accepted. The default value of WEL is 0.
BP2, BP1, BP0 bits.
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected
against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command. When the
Block Protect (BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in Table1).becomes protected against
Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block Protect (BP2, BP1, BP0) bits can be
written provided that the Hardware Protected mode has not been set. The Chip Erase (CE) command is executed, if the
Block Protect (BP2, BP1, BP0) bits are all 0. The default value of BP2:0 are 0s.
SRP bit
The Status Register Protect (SRP) bit operates in conjunction with the Write Protect (WP#) signal. The Status Register
Write Protect (SRP) bit and Write Protect (WP#) signal set the device to the Hardware Protected mode. When the Status
Register Protect (SRP) bit is set to 1, and Write Protect (WP#) is driven Low. In this mode, the non-volatile bits of the Status
Register(SRP, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is not execution.
The default value of SRP is 0.




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