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GD25D10CPFG Datasheet(Scheda tecnica) 19 Page - GigaDevice Semiconductor (Beijing) Inc.

Numero della parte GD25D10CPFG
Dettagli  3.3V Uniform Sector Standard and Dual Serial Flash
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Produttore  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
Homepage  http://www.gigadevice.com/
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 19 page
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3.3V Uniform Sector
Standard and Dual Serial Flash
GD25D10C/05C
19
Figure11. 64KB Block Erase Sequence Diagram
7.12. Chip Erase (CE) (60/C7H)
The Chip Erase (CE) command is for erasing the all data of the chip. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE) command is entered by driving
CS# Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of the
sequence.
The Chip Erase command sequence: CS# goes low  sending Chip Erase command  CS# goes high. The
command sequence is shown in Figure12. CS# must be driven high after the eighth bit of the command code has been
latched in, otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the self-timed Chip Erase
cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check
the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and
is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
The Chip Erase (CE) command is executed if the Block Protect (BP2, BP1, BP0) bits are all 0. The Chip Erase (CE)
command is not executed if any sector is under protection.
Figure12. Chip Erase Sequence Diagram
7.13. Deep Power-Down (DP) (B9H)
Executing the Deep Power-Down (DP) command is the only way to enter the lowest consumption mode (the Deep
Power-Down Mode). Unlike deselecting the device by driving CS# high, or entering into the Standby Mode (if there is no
internal cycle currently in progress), the Deep Power-Down Mode provides an extra software protection mechanism while
the device is not in active use. The only access to this mode is by executing the Deep Power-Down (DP) command. Since
in the Deep Power-Down mode, the device ignores all Write, Program and Erase commands. Once the device is in the
Deep Power-Down Mode, all commands are ignored except the Release from Deep Power-Down and Read Device ID (RDI)
command. The Release from Deep Power-Down and Read Device ID (RDI) command releases the device from Deep
Power-Down mode, also allows the Device ID of the device to be output on SO.
The Deep Power-Down Mode automatically stops at Power-Down, and the device is in the Standby Mode after Power-
Up.
Command
0
1
2
3
4
5
6
7
60H or C7H
CS#
SCLK
SI
Command
0
1
2
3
4
5
6
7
D8H
CS#
SCLK
SI
8
9
29 30 31
MSB
2
1
0
24 Bits Address
23 22




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