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GD25LB32D Scheda tecnica(PDF) 53 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25LB32D Scheda tecnica(HTML) 53 Page - GigaDevice Semiconductor (Beijing) Inc. |
53 / 67 page 1.8V Uniform Sector Dual and Quad Serial Flash GD25LB32D 53 7.37. Enable Reset (66H) and Reset (99H) If the Reset command is accepted, any on-going internal operation will be terminated and the device will return to its default power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch status (WEL), Program/Erase Suspend status, Read Parameter setting (P7-P0), Deep Power Down Mode, Continuous Read Mode bit setting (M7-M0) and Wrap Bit Setting (W6-W4). The “Enable Reset (66H)” and the “Reset (99H)” commands can be issued in either SPI or QPI mode. The “Reset (99H) ” command sequence as follow: CS# goes low Sending Enable Reset command CS# goes high CS# goes low Sending Reset command CS# goes high. Once the Reset command is accepted by the device, the device will take approximately tRST =30us / tRST_E =12ms to reset. During this period, no command will be accepted. Data corruption may happen if there is an on-going or suspended internal Erase or Program operation when Reset command sequence is accepted by the device. It is recommended to check the BUSY bit and the SUS bit in Status Register before issuing the Reset command sequence. Figure37. Enable Reset and Reset command Sequence Diagram Command 0 1 2 3 4 5 6 7 66H CS# SCLK SI SO High-Z Command 0 1 2 3 4 5 6 7 99H Figure38. Enable Reset and Reset command Sequence Diagram (QPI) CS# SCLK IO0 IO1 IO2 IO3 0 1 Command 66H 0 1 Command 99H |
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