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GD25LB32D Scheda tecnica(PDF) 48 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25LB32D Scheda tecnica(HTML) 48 Page - GigaDevice Semiconductor (Beijing) Inc. |
48 / 67 page 1.8V Uniform Sector Dual and Quad Serial Flash GD25LB32D 48 7.31. Program Security Registers (42H) The Program Security Registers command is similar to the Page Program command. Each security register contains four pages content. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Program Security Registers command. The Program Security Registers command is entered by driving CS# Low, followed by the command code (42H), three address bytes and at least one data byte on SI. As soon as CS# is driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is initiated. While the Program Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. If the Security Registers Lock Bit (LB3-1) is set to 1, the Security Registers will be permanently locked. Program Security Registers command will be ignored. Address A23-16 A15-12 A11-10 A9-0 Security Register #1 00H 0 0 0 1 0 0 Byte Address Security Register #2 00H 0 0 1 0 0 0 Byte Address Security Register #3 00H 0 0 1 1 0 0 Byte Address Figure31. Program Security Registers command Sequence Diagram Command 0 1 2 3 4 5 6 7 42H CS# SCLK SI 8 9 10 28 29 30 31 3 2 1 0 23 22 21 24-bit address 42 43 44 45 41 46 47 40 50 51 52 53 49 54 55 48 6 5 4 3 2 1 0 7 CS# SCLK SI MSB Data Byte 2 32 33 34 35 7 6 5 4 3 2 1 0 MSB 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 Data Byte 1 Data Byte 3 Data Byte 256 MSB MSB 36 37 38 39 MSB |
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