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GD25LB32D Scheda tecnica(PDF) 47 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25LB32D Scheda tecnica(HTML) 47 Page - GigaDevice Semiconductor (Beijing) Inc. |
47 / 67 page 1.8V Uniform Sector Dual and Quad Serial Flash GD25LB32D 47 7.30. Erase Security Registers (44H) The GD25LB32D provides three 1024-byte Security Registers which can be erased and programmed individually. These registers may be used by the system manufacturers to store security and other important information separately from the main memory array. The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The Erase Security Registers command sequence: CS# goes low sending Erase Security Registers command 3-byte address on SI CS# goes high. The command sequence is shown in Figure30. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the Erase Security Registers command is not executed. As soon as CS# is driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the Erase Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Security Registers Lock Bit (LB3-1) in the Status Register can be used to OTP protect the security registers. Once the LB bit is set to 1, the Security Registers will be permanently locked; the Erase Security Registers command will be ignored. Address A23-16 A15-12 A11-10 A9-0 Security Register #1 00H 0 0 0 1 0 0 Don ’t care Security Register #2 00H 0 0 1 0 0 0 Don ’t care Security Register #3 00H 0 0 1 1 0 0 Don ’t care Figure30. Erase Security Registers command Sequence Diagram Command 0 1 2 3 4 5 6 7 44H CS# SCLK SI 8 9 29 30 31 MSB 2 1 0 24 Bits Address 23 22 |
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