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GD25LB32D Scheda tecnica(PDF) 36 Page - GigaDevice Semiconductor (Beijing) Inc.

Il numero della parte GD25LB32D
Spiegazioni elettronici  1.8V Uniform Sector Dual and Quad Serial Flash
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Produttore elettronici  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
Homepage  http://www.gigadevice.com/
Logo GIGADEVICE - GigaDevice Semiconductor (Beijing) Inc.

GD25LB32D Scheda tecnica(HTML) 36 Page - GigaDevice Semiconductor (Beijing) Inc.

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1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LB32D
36
7.20.
Chip Erase (CE) (60/C7H)
The Chip Erase (CE) command is erased the all data of the chip. A Write Enable (WREN) command must previously
have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE) command is entered by driving CS#
Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of the
sequence.
The Chip Erase command sequence: CS# goes low  sending Chip Erase command  CS# goes high. The
command sequence is shown in Figure20. CS# must be driven high after the eighth bit of the command code has been
latched in; otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the self-timed Chip Erase
cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be read to
check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Chip Erase
cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL)
bit is reset. The Chip Erase (CE) command is executed if the Block Protect (BP2, BP1, and BP0) bits are 0 and CMP=0 or
the Block Protect (BP2, BP1, and BP0) bits are 1 and CMP=1. The Chip Erase (CE) command is ignored if one or more
sectors are protected.
Figure20. Chip Erase Sequence Diagram
Command
0
1
2
3
4
5
6
7
60H or C7H
CS#
SCLK
SI
Figure20a. Chip Erase Sequence Diagram (QPI)
CS#
SCLK
IO0
IO1
IO2
IO3
0
1
Instruction
C7H/60H


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