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GD25LB32D Scheda tecnica(PDF) 34 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25LB32D Scheda tecnica(HTML) 34 Page - GigaDevice Semiconductor (Beijing) Inc. |
34 / 67 page 1.8V Uniform Sector Dual and Quad Serial Flash GD25LB32D 34 7.18. 32KB Block Erase (BE) (52H) The 32KB Block Erase (BE) command is erased the all data of the chosen block. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block is a valid address for the 32KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence. The 32KB Block Erase command sequence: CS# goes low sending 32KB Block Erase command 3-byte address on SI CS# goes high. The command sequence is shown in Figure18. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 32KB Block Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tSE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A 32KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits (see Table1&1a) is not executed. Figure18. 32KB Block Erase Sequence Diagram Command 0 1 2 3 4 5 6 7 52H CS# SCLK SI 8 9 29 30 31 MSB 2 1 0 24 Bits Address 23 22 Figure18a. 32KB Block Erase Sequence Diagram (QPI) CS# SCLK IO0 IO1 IO2 IO3 0 1 2 3 4 5 Command 52H 20 12 16 8 A23-16 A12-8 6 7 0 21 13 17 9 1 23 15 19 11 3 22 14 18 10 2 4 5 6 7 A7-0 |
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