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GD25LB32D Scheda tecnica(PDF) 23 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25LB32D Scheda tecnica(HTML) 23 Page - GigaDevice Semiconductor (Beijing) Inc. |
23 / 67 page 1.8V Uniform Sector Dual and Quad Serial Flash GD25LB32D 23 7.8. Fast Read (0BH) in QPI mode The Fast Read command is also supported in QPI mode. In QPI mode, the number of dummy clocks is configured by the “Set Read Parameters (C0H)” command to accommodate a wide range application with different needs for either maximum Fast Read frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either 4/6/8. Figure8a. Read Data Bytes at Higher Speed Sequence Diagram (QPI) CS# SCLK IO0 IO1 IO2 IO3 0 1 2 3 4 5 Command 0BH 20 12 16 8 6 7 8 9 10 4 4 0 0 4 0 4 0 4 21 13 17 9 5 5 1 1 5 1 5 1 5 22 14 18 10 6 6 2 2 6 2 6 2 6 23 15 19 11 7 7 3 3 7 3 7 3 7 A23-16 A15-8 A7-0 Dummy* 11 12 13 IOs switch from Input to output Byte1 *"Set Read Parameters" Command (C0H) can set the number of dummy clocks Dummy* 7.9. Dual Output Fast Read (3BH) The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, and each bit is latched in on the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command sequence is shown in followed Figure9. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure9. Dual Output Fast Read Sequence Diagram Command 0 1 2 3 4 5 6 7 3BH CS# SCLK SI SO High-Z 8 9 10 28 29 30 31 3 2 1 0 23 22 21 24-bit address MSB 34 35 36 37 33 5 3 1 7 5 3 1 38 39 Data Out1 32 42 43 44 45 41 46 47 40 7 Data Out2 CS# SCLK SI SO MSB Dummy Clocks 4 2 0 6 4 2 0 6 6 7 |
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