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GD25LB32D Scheda tecnica(PDF) 18 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25LB32D Scheda tecnica(HTML) 18 Page - GigaDevice Semiconductor (Beijing) Inc. |
18 / 67 page 1.8V Uniform Sector Dual and Quad Serial Flash GD25LB32D 18 7.2. Write Disable (WRDI) (04H) The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence: CS# goes low Sending the Write Disable command CS# goes high. The WEL bit is reset by following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase, Chip Erase, Erase/Program Security Registers and Reset commands. Figure3. Write Disable Sequence Diagram Command 0 1 2 3 4 5 6 7 04H CS# SCLK SI SO High-Z Figure3a. Write Disable Sequence Diagram (QPI) CS# SCLK IO0 IO1 IO2 IO3 0 1 Command 04H |
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