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GD25D05C Datasheet(Scheda tecnica) 14 Page - GigaDevice Semiconductor (Beijing) Inc.

Numero della parte GD25D05C
Dettagli  3.3V Uniform Sector Standard and Dual Serial Flash
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Produttore  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
Homepage  http://www.gigadevice.com/
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 14 page
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3.3V Uniform Sector
Standard and Dual Serial Flash
GD25D10C/05C
14
Figure3. Read Status Register Sequence Diagram
7.4. Write Status Register (WRSR) (01H)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. A Write Enable
(WREN) instruction must be executed previously to set the Write Enable Latch (WEL) bit, before it can be accepted.
The Write Status Register (WRSR) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction
code and the data byte on Serial Data Input (DI).
The Write Status Register (WRSR) instruction has no effect on S6, S5, S1 and S0 of the Status Register. S6 and S5
are always read as 0. Chip Select (CS#) must be driven High after the eighth bit of the data byte has been latched in.
Otherwise, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (CS#) is driven High, the
self-timed Write Status Register cycle (the duration is tW) is initiated. While the Write Status Register cycle is in progress,
reading Status Register to check the Write In Progress (WIP) bit is achievable.
The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and turn to 0 on the completion
of the Write Status Register. When the cycle is completed, the Write Enable Latch (WEL) is reset to 0.
The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP2, BP1,
BP0) bits, which are utilized to define the size of the read-only area.
The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Protect (SRP)
bit in accordance with the Write Protect (WP#) signal, by setting which the device can enter into Hardware Protected Mode
(HPM). The Write Status Register (WRSR) instruction is not executed once enter into the Hardware Protected Mode (HPM).
Figure4. Write Status Register Sequence Diagram
Command
0
1
2
3
4
5
6
7
05H
CS#
SCLK
SI
SO
High-Z
8
9 10 11 12 13 14 15
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
S7~S0 out
S7~S0 out
MSB
Command
0
1
2
3
4
5
6
7
01H
CS#
SCLK
SI
SO
High-Z
8
9 10 11 12 13 14 15
MSB
7
6
5
4
3
2
1
0
Status Register in




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