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GD25B257D Scheda tecnica(PDF) 55 Page - GigaDevice Semiconductor (Beijing) Inc.

Il numero della parte GD25B257D
Spiegazioni elettronici  3.3V Uniform Sector Dual and Quad Serial Flash
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Produttore elettronici  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
Homepage  http://www.gigadevice.com/
Logo GIGADEVICE - GigaDevice Semiconductor (Beijing) Inc.

GD25B257D Scheda tecnica(HTML) 55 Page - GigaDevice Semiconductor (Beijing) Inc.

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3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B257D
55
8.22.
Chip Erase (CE) (60/C7H)
The Chip Erase (CE) command is erased the all data of the chip. A Write Enable (WREN) command must previously
have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE) command is entered by driving CS#
Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of the
sequence.
The Chip Erase command sequence: CS# goes low  sending Chip Erase command  CS# goes high. CS# must
be driven high after the eighth bit of the command code has been latched in; otherwise the Chip Erase command is not
executed. As soon as CS# is driven high, the self-timed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip
Erase cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write
in Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and is 0 when it is completed. At some unspecified time
before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Chip Erase (CE) command is ignored if one
or more sectors/blocks are protected.
Figure 57. Chip Erase Sequence Diagram
Command
0
1
2
3
4
5
6
7
60H or C7H
CS#
SCLK
SI


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