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GD25B256D Scheda tecnica(PDF) 30 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25B256D Scheda tecnica(HTML) 30 Page - GigaDevice Semiconductor (Beijing) Inc. |
30 / 82 page 3.3V Uniform Sector Dual and Quad Serial Flash GD25B256D 30 Figure 20 Quad Output Fast Read Sequence Diagram (ADS=1) Note: 1. The dummy clock number is configurable. Command 0 1 2 3 4 5 6 7 6BH CS# SCLK SI(IO0) SO(IO1) High-Z 8 9 10 36 37 38 39 3 2 1 0 31 30 29 32-bit address 1 5 1 5 1 5 1 Byte1 5 Dummy Clocks 0 4 0 4 0 4 0 4 4 5 IO2 High-Z IO3 High-Z CS# SCLK SI(IO0) SO(IO1) IO2 IO3 2 6 2 6 2 6 2 6 6 3 7 3 7 3 7 3 7 7 Byte2 Byte3 Byte4 42 43 44 45 41 46 47 40 50 51 52 53 49 54 55 48 |
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