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GD25B256D Scheda tecnica(PDF) 28 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25B256D Scheda tecnica(HTML) 28 Page - GigaDevice Semiconductor (Beijing) Inc. |
28 / 82 page 3.3V Uniform Sector Dual and Quad Serial Flash GD25B256D 28 Figure 18 Dual Output Fast Read with 4-Byte Address Sequence Diagram (ADS=0 or ADS=1) Note: 1. The dummy clock number is configurable. Command 0 1 2 3 4 5 6 7 3CH CS# SCLK SI SO High-Z 8 9 10 36 37 38 39 3 2 1 0 31 30 29 32-bit address MSB 42 43 44 45 41 5 3 1 46 47 Data Out1 40 50 51 52 53 49 54 55 48 7 6 5 4 3 2 1 0 7 Data Out2 CS# SCLK SI SO MSB Dummy Byte 6 4 2 0 5 3 1 7 6 4 2 0 6 7 |
Codice articolo simile - GD25B256D |
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Descrizione simile - GD25B256D |
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