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GD25B127D Datasheet(Scheda tecnica) 11 Page - GigaDevice Semiconductor (Beijing) Inc.

Numero della parte GD25B127D
Dettagli  3.3V Uniform Sector Dual and Quad Serial Flash
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Produttore  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
Homepage  http://www.gigadevice.com/
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3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
11
6. STATUS REGISTER
S23
S22
S21
S20
S19
S18
S17
S16
Reserved
DRV1
DRV0
Reserved
Reserved
Reserved
Reserved
Reserved
S15
S14
S13
S12
S11
S10
S9
S8
SUS1
CMP
LB3
LB2
LB1
SUS2
QE
SRP1
S7
S6
S5
S4
S3
S2
S1
S0
SRP0
BP4
BP3
BP2
BP1
BP0
WEL
WIP
The status and control bits of the Status Register are as follows:
WIP bit.
The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress.
When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0,
means the device is not in program/erase/write status register progress.
WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal
Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or
Erase command is accepted.
BP4, BP3, BP2, BP1, BP0 bits.
The Block Protect (BP4, BP3, BP2, BP1 and BP0) bits are non-volatile. They define the size of the area to be software
protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command.
When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in
Table1).becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Chip
Erase (CE) command is executed, if the Block Protect (BP2, BP1, and BP0) bits are 0 and CMP=0 or the Block Protect
(BP2, BP1, and BP0) bits are 1 and CMP=1.
SRP1, SRP0 bits.
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP
bits control the method of write protection: software protection, power supply lock-down or one time programmable
protection.
SRP1
SRP0
Status Register
Description
0
0
Software Protected
The Status Register can be written to after a Write Enable
command, WEL=1. (Default)
1
0
Power Supply Lock-Down(1)(2)
Status Register is protected and cannot be written to again
until the next Power-Down, Power-Up cycle.
1
1
One Time Program(2)
Status Register is permanently protected and cannot be
written to.
NOTE:
1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.
2. This feature is available on special order. Please contact GigaDevice for details.
QE bit.
The Quad Enable (QE) bit is a non-volatile bit in the Status Register that allows Quad operation. The default value of
QE bit is 1 and it cannot be changed, so that the Quad IO2 and IO3 pins are enabled all the time.




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