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GD25B16C Scheda tecnica(PDF) 23 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25B16C Scheda tecnica(HTML) 23 Page - GigaDevice Semiconductor (Beijing) Inc. |
23 / 53 page 3.3V Uniform Sector Dual and Quad Serial Flash GD25B16C 23 7.12. Quad I/O Word Fast Read (E7H) The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest address bit (A0) must equal 0 and only 2-dummy clock. The command sequence is shown in followed Figure14. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Word Fast read command. Quad I/O Word Fast Read with “Continuous Read Mode” The Quad I/O Word Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0) =AXH, then the next Quad I/O Word Fast Read command (after CS# is raised and then lowered) does not require the E7H command code. The command sequence is shown in followed Figure15. If the “Continuous Read Mode” bits (M7-0) are any value other than AXH, the next command requires the first E7H command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M7-0) before issuing normal command. Figure 14. Quad I/O Word Fast Read Sequence Diagram (M7-0= 0XH or not AXH) Figure 15. Quad I/O Word Fast Read Sequence Diagram (M7-0= AXH) Command 0 1 2 3 4 5 6 7 E7H CS# SCLK IO0 IO1 8 9 10 11 12 13 14 15 4 0 4 0 4 0 4 0 16 17 18 19 20 21 22 23 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 A23-16 A15-8 A7-0 M7-0 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 IO2 IO3 4 5 6 7 Dummy Byte1 Byte2 4 0 5 1 6 2 7 3 Byte3 0 1 2 3 4 5 6 7 CS# SCLK 8 9 10 11 12 13 14 15 IO0 IO1 IO2 IO3 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 5 6 7 A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 4 0 5 1 6 2 7 3 Byte3 |
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