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GD25B16C Datasheet(Scheda tecnica) 19 Page - GigaDevice Semiconductor (Beijing) Inc.

Numero della parte GD25B16C
Dettagli  3.3V Uniform Sector Dual and Quad Serial Flash
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Produttore  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
Homepage  http://www.gigadevice.com/
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 19 page
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3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B16C
19
Figure 7. Read Data Bytes at Higher Speed Sequence Diagram
7.8. Dual Output Fast Read (3BH)
The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being
latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO.
The command sequence is shown in followed Figure 8. The first byte addressed can be at any location. The address is
automatically incremented to the next higher address after each byte of data is shifted out.
Figure 8. Dual Output Fast Read Sequence Diagram
7.9. Quad Output Fast Read (6BH)
The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being
latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1
and IO0. The command sequence is shown in followed Figure 9. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out.
Command
0
1
2
3
4
5
6
7
0BH
CS#
SCLK
SI
SO
High-Z
8
9 10
28 29 30 31
3
2
1
0
23 22 21
24-bit address
MSB
34 35 36 37
33
6
5
4
3
2
1
0
38 39
Data Out1
32
42 43 44 45
41
46 47
40
7
6
5
4
3
2
1
0
7
6
5
7
Data Out2
CS#
SCLK
SI
SO
MSB
Dummy Byte
Command
0
1
2
3
4
5
6
7
3BH
CS#
SCLK
SI
SO
High-Z
8
9 10
28 29 30 31
3
2
1
0
23 22 21
24-bit address
MSB
34 35 36 37
33
5
3
1
7
5
3
1
38 39
Data Out1
32
42 43 44 45
41
46 47
40
7
Data Out2
CS#
SCLK
SI
SO
MSB
Dummy Clocks
4
2
0
6
4
2
0
6
6
7




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