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GD5F2GQ4RE9FG Scheda tecnica(PDF) 8 Page - GigaDevice Semiconductor (Beijing) Inc.

Il numero della parte GD5F2GQ4RE9FG
Spiegazioni elettronici  SPI(x1/x2/x4) NAND Flash
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Produttore elettronici  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
Homepage  http://www.gigadevice.com/
Logo GIGADEVICE - GigaDevice Semiconductor (Beijing) Inc.

GD5F2GQ4RE9FG Scheda tecnica(HTML) 8 Page - GigaDevice Semiconductor (Beijing) Inc.

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SPI(x1/x2/x4) NAND Flash
2G
8
3
ARRAY ORGANIZATION
Each device has
Each block has
Each page has
2G
256M+16M
128K+8K
2K+128
bytes
2048 x 64
64
-
pages
2048
-
-
blocks
Figure3-1. Array Organization
2048
128
2048
128
1 block
1 block = (2K + 128 bytes) x 64 pages
= (128K + 8K) bytes
1 page
= (2K + 128 bytes)
Cache Register
Data Register
SO
SI
Per device:
2Gb: 2048blocks
1 device:
For 2Gb = (128K + 8K) bytes x 2048 blocks
= 1Gb
Internal ECC = OFF
2048
64
2048
64
1 block
1 block = (2K + 64 bytes) x 64 pages
= (128K + 4K) bytes
1 page
= (2K + 64 bytes)
Cache Register
Data Register
SO
SI
Per device:
2Gb: 2048blocks
1 device:
For 2Gb = (128K + 4K) bytes x 2048 blocks
= 2Gb
Internal ECC= ON
Note:
1.When Internal ECC is enabled，user can program the first 64 bytes of the entire 128 bytes spare area and the
last 64 bytes of the whole spare area cannot be programed，user can read the entire 128 Byte spare area.
2.When Internal ECC is disabled，user can read and program the entire 128 bytes spare area.


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