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MAX2165 Datasheet(Scheda tecnica) 8 Page - Maxim Integrated Products
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MAXIM [Maxim Integrated Products]
The MAX2165 includes 15 programmable registers and
three read-only registers. See Table 1 for register con-
figurations. The register configuration of Table 1 shows
each bit name and the bit usage information for all reg-
isters. U labeled under each bit name indicates that the
bit value is user defined to meet specific application
requirements. A 0 or 1 indicates that the bit must be set
to the defined 0 or 1 value for proper operation.
Operation is not tested or guaranteed if these bits are
programmed to other values and is only for
factory/bench evaluation. In typical application, always
program to the operation defined state.
See Tables 2–19 for detailed descriptions of each reg-
ister. All registers must be written 100µs after power-up
and no earlier than 100µs after power-up.
Single-Conversion DVB-H Tuner
Pin Description (continued)
Noninverting Quadrature Baseband Output
Inverting In-Phase Baseband Output
Noninverting In-Phase Baseband Output
Baseband Gain-Control Voltage Input. Accepts voltages from 0.4V to 2.3V with 2.3V providing the
maximum baseband gain.
VCO Power-Supply Input. Connect to a low-noise power-supply voltage. Bypass to the PCB ground
plane with a 1000pF and 100nF capacitor placed as close as possible to the pin.
VCO Tuning Voltage Input. Connect to the PLL loop filter output.
VCO Tuning Voltage Ground. Connect to the PCB ground plane.
VCO Linear-Regulator Noise Bypass. Bypass to the PCB ground plane with a 470nF capacitor placed
as close as possible to the pin.
Charge-Pump Output. Connect to the PLL loop filter input.
Synthesizer Power-Supply Input. Connect to a low-noise power-supply voltage. Bypass to the PCB
ground plane with a 1000pF and 100nF capacitor placed as close as possible to the pin.
Multiplexed Output Line. Output for various test functions, can also be used as a PLL lock-detect
indicator. See Table 9 for more information. When used as a PLL lock detector, logic-high indicates
PLL is not locked and logic-low indicates PLL is locked.
Reference Buffer Output. Provides a buffered crystal-oscillator signal that can be used as a clock
reference for the demodulator. Requires a DC-blocking capacitor.
Crystal-Oscillator Power-Supply Input. Connect to a low-noise power-supply voltage. Bypass to the
PCB ground plane with a 1000pF and 100nF capacitor placed as close as possible to the pin.
Reference Input. Connect to a parallel resonant mode crystal through a load-matching capacitor or to
a reference oscillator.
Reference-Oscillator Feedback Input. Connect to a capacitive feedback network when the on-chip
reference oscillator is used. Leave unconnected when an external reference is used.
Exposed Paddle. Solder evenly to the board’s ground plane to achieve the lowest impedance path.
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