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EMD04N08E Scheda tecnica(PDF) 1 Page - Excelliance MOS Corp. |
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EMD04N08E Scheda tecnica(HTML) 1 Page - Excelliance MOS Corp. |
1 / 6 page 2015/10/22 p.1 EMD04N08E G D S N‐Channel Logic Level Enhancement Mode Field Effect Transistor Product Summary: BVDSS 80V RDSON (MAX.) 4.6mΩ ID 160A UIS, Rg 100% Tested Pb‐Free Lead Plating & Halogen Free ABSOLUTE MAXIMUM RATINGS (TA = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS SYMBOL LIMITS UNIT Gate‐Source Voltage VGS ±30 V Continuous Drain Current TC = 25 °C ID 160 A TC = 100 °C 126 Pulsed Drain Current 1 IDM 540 Avalanche Current IAS 90 Avalanche Energy L = 0.1mH, ID=90A, RG=25Ω EAS 405 mJ Repetitive Avalanche Energy 2 L = 0.05mH EAR 202 Power Dissipation TC = 25 °C PD 250 W TC = 100 °C 100 Operating Junction & Storage Temperature Range Tj, Tstg ‐55 to 150 °C 100% UIS testing in condition of VD=30V, L=0.1mH, VG=10V, IL=60A, Rated VDS=80V N-CH THERMAL RESISTANCE RATINGS THERMAL RESISTANCE SYMBOL TYPICAL MAXIMUM UNIT Junction‐to‐Case RJC 0.50 °C / W Junction‐to‐Ambient RJA 60 1Pulse width limited by maximum junction temperature. 2Duty cycle 1% |
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