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SF5773 Scheda tecnica(PDF) 2 Page - SIFIRST TECHNOLOGIES NANHAI LIMITED |
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SF5773 Scheda tecnica(HTML) 2 Page - SIFIRST TECHNOLOGIES NANHAI LIMITED |
2 / 2 page ©SiFirst Technology - 2 - Confidential SiFirst_DS_5773_V1.0 SF5773 Pin Configuration Ordering Information Part Number Top Mark Package Tape & Reel SF5773LGT .73YWW SOT26 Green Yes Marking Information Pin Description Pin Num Pin Name I/O Description 1 GND P IC ground pin. 2 FB I Voltage feedback pin. The loop regulation is achieved by connecting a photo-coupler to this pin. PWM duty cycle is generated by this pin voltage and the current sense signal at Pin 4. 3 DEM I Transformer core demagnetization detection pin. This pin is also used for output over voltage protection (Output OVP). 4 CS I Current sense input pin. 5 VDD P IC power supply pin. 6 GATE O Totem-pole gate driver output to drive the external MOSFET. |
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