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H27UCG8T2BTR-BC Scheda tecnica(PDF) 36 Page - Hynix Semiconductor |
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H27UCG8T2BTR-BC Scheda tecnica(HTML) 36 Page - Hynix Semiconductor |
36 / 56 page H27UCG8T2BTR-BC 64Gb(8192M x 8bit) MLC NAND Flash Rev 0.1 / Oct. 2012 36 3.22. Multi-Plane Cache Program Operation Timings CLE WE# ALE R/B# Col. Add1 80h Col. Add2 Row. Add1 Row. Add2 Row. Add3 DIN N DIN M I/Ox CE# tWC tDBSY 11h Col. Add1 81h Col. Add2 Row. Add1 Row. Add2 Row. Add3 DIN N DIN M tWC 15h A tCBSYW tWB tADL tADL : Don’t care CLE WE# ALE R/B# Col. Add1 80h Col. Add2 Row. Add1 Row. Add2 Row. Add3 DIN N DIN M I/Ox CE# tWC tDBSY 11h Col. Add1 81h Col. Add2 Row. Add1 Row. Add2 Row. Add3 DIN N DIN M tWC 10h A tPROG tWB tADL tADL A0-A14 : Valid A15-A22 : Valid (Page M) A23 : Fixed ‘Low’ A24 ~ A34 : Valid (Block J) A0-A14 : Valid A15-A22 : Valid( Page M) A23 : Fixed ‘High’ A24 ~ A34 : Valid (Block K) A0-A14 : Valid A15-A22 : Valid( Page M+n) A23 : Fixed ‘Low’ A24 ~ A34 : Valid (Block J) A0-A14 : Valid A15-A22 : Valid( Page M+n) A23 : Fixed ‘High’ A24 ~ A34 : Valid (Block K) Figure 28 : Multi-plane cache program operation timings Notes: 1. tPROG = Program time for the last page + Program time for the (last -1)th page – (command input cycle time + address input cycle time + Last page data loading time) 2. Make sure to terminate the operation with 80h-10h- command sequence. If the operation is terminated by 80h-15h command sequences, monitor I/O5 (Ready/Busy) and I/O6 (Data Cache Ready/Busy) by issuing Read Status Command (70h) and make sure the previous and current Cache Page Program operation is completed. If the page program operation is completed, issue FFh reset before next operation. 3. Selected Page address except A23 within two blocks must be same. 3.23. Block Erase Operation Timings Figure 29 : Block erase operation timings |
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