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INA819 Scheda tecnica(PDF) 27 Page - Texas Instruments |
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INA819 Scheda tecnica(HTML) 27 Page - Texas Instruments |
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27 / 43 page  + ± + ± + ± 40 k 25 k 40 k 40 k 40 k 25 k Overvoltage Protection Overvoltage Protection RG REF +VS V- OUT V+ -VS -IN +IN RG RREF RG 27 INA819 www.ti.com SBOS959 – DECEMBER 2018 Product Folder Links: INA819 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information 9.1.1 Reference Pin The output voltage of the INA819 is developed with respect to the voltage on the reference pin (REF.) In dual- supply operation, the reference pin (pin 6) is connected to the low-impedance system ground. In single-supply operation, offsetting the output signal to a precise midsupply level is useful (for example, 2.5 V in a 5-V supply environment). To accomplish this level shift, a voltage source must be connected to the REF pin to level-shift the output so that the INA819 drives a single-supply ADC. The voltage source applied to the reference pin must have a low output impedance. As shown in Figure 65, any resistance at the reference pin (shown as RREF in Figure 65) is in series with an internal 40-kΩ resistor. Figure 65. Parasitic Resistance Shown at the Reference Pin The parasitic resistance at the reference pin (RREF) creates an imbalance in the four resistors of the internal difference amplifier, which degrades the common-mode rejection ratio (CMRR). Figure 66 shows the degradation in CMRR of the INA819 as a result of increased resistance at the reference pin. For the best performance, keep the source impedance to the REF pin (RREF) below 5 Ω. |
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