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AD5382 Scheda tecnica(PDF) 7 Page - Analog Devices |
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AD5382 Scheda tecnica(HTML) 7 Page - Analog Devices |
7 / 40 page AD5382 Rev. 0 | Page 7 of 40 Parameter AD5382-31 Unit Test Conditions/Comments LOGIC OUTPUTS (BUSY, SDO)3 VOL, Output Low Voltage 0.4 V max Sinking 200 µA VOH, Output High Voltage DVDD – 0.5 V min Sourcing 200 µA High Impedance Leakage Current ±1 µA max SDO only High Impedance Output Capacitance 5 pF typ SDO only LOGIC OUTPUT (SDA)3 VOL, Output Low Voltage 0.4 V max ISINK = 3 mA 0.6 V max ISINK = 6 mA Three-State Leakage Current ±1 µA max Three-State Output Capacitance 8 pF typ POWER REQUIREMENTS AVDD 2.7/3.6 V min/max DVDD 2.7/5.5 V min/max Power Supply Sensitivity3 ∆Midscale/∆ΑVDD –85 dB typ AIDD 0.375 mA/channel max Outputs unloaded, Boost off. 0.25 mA/channel typ 0.475 mA/channel max Outputs unloaded, Boost on. 0.325 mA/channel typ DIDD 1 mA max VIH = DVDD, VIL = DGND. AIDD (Power-Down) 2 µA max DIDD (Power-Down) 20 µA max Power Dissipation 39 mW max Outputs unloaded, Boost off, AVDD = DVDD = 3 V 1 AD5382-3 is calibrated using an external 1.25 V reference. Temperature range is –40°C to +85°C. 2 Accuracy guaranteed from VOUT = 10 mV to AVDD – 50 mV. 3 Guaranteed by characterization, not production tested. 4 Default on the AD5382-5 is 2.5 V. Programmable to 1.25 V via CR12 in the AD5382 control register; operating the AD5382-5 with a 1.25 V reference leads to degraded accuracy specifications. AC CHARACTERISTICS1 Table 5. AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V; AGND = DGND= 0 V Parameter All Unit Test Conditions/Comments DYNAMIC PERFORMANCE Output Voltage Settling Time 2 1/4 scale to 3/4 scale change settling to ±1 LSB. 8 µs typ 10 µs max Slew Rate2 2 V/µs typ Boost mode off, CR11 = 0 3 V/µs typ Boost mode on, CR11 = 1 Digital-to-Analog Glitch Energy 12 nV-s typ Glitch Impulse Peak Amplitude 15 mV typ Channel-to-Channel Isolation 100 dB typ See Terminology section DAC-to-DAC Crosstalk 1 nV-s typ See Terminology section Digital Crosstalk 0.8 nV-s typ Digital Feedthrough 0.1 nV-s typ Effect of input bus activity on DAC output under test Output Noise 0.1 Hz to 10 Hz 15 µV p-p typ External reference, midscale loaded to DAC 40 µV p-p typ Internal reference, midscale loaded to DAC Output Noise Spectral Density @ 1 kHz 150 nV/√Hz typ @ 10 kHz 100 nV/√Hz typ 1 Guaranteed by design and characterization, not production tested. 2 The slew rate can be programmed via the current boost control bit (CR11 ) in the AD5382 control register. |
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