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LM1236 Scheda tecnica(PDF) 10 Page - National Semiconductor (TI) |
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LM1236 Scheda tecnica(HTML) 10 Page - National Semiconductor (TI) |
10 / 43 page Typical Performance Characteristics V CC =5V, TA = 25˚C unless otherwise specified (Continued) TABLE 3. OSD Register Recommendations PPL=0 PPL=1 PPL=2 PPL=3 PPL=4 PPL=5 PPL=6 PPL=7 PLL Auto 25 - 110 25 - 110 25 - 110 25 - 110 25 - 110 25 - 108 25 - 102 25 - 96 If 1152 pixels per line is being used, the horizontal scan rate would have to be lower than 106 kHz in order to not exceed the maximum OSD pixel frequency of 111 MHz. The maxi- mum number of vertical video lines that may be used is 1536 lines as in a 2048x1536 display. The LM1236 has a PLL Auto feature, which will automatically select an internal PLL frequency range setting that will guarantee optimal OSD locking for any horizontal scan rate. This offers improved PLL performance and eliminates the need for PLL register settings determined by the user. To initialize the PLL Auto feature, set bits, 0x843E[1:0] to 0 for pre-calibration, which takes one vertical scan period to complete, and must be done while the video is blanked. Subsequently, set 0x843E[6] to 1, which must also be done while the video is blanked. Table 3 shows the recommended horizontal scan rate ranges (in kHz) for each pixels per line register setting, 0x8401[7:5]. These ranges are recommended for chip am- bient temperatures of 0oCto70oC, and the recommended PLL filter values are 6.2kohms, 0.01uF, and 1000pF as shown in the schematic. While the OSD PLL will lock for other register combinations and at scan rates outside these ranges, the performance of the loop will be improved if these recommendations are followed. PLL Auto Mode Initialization Sequence • Blank video • In PLL manual mode, set PLL range (0x843E[1:0]) to 0 • Wait for at least one vertical period or vertical sync pulse to pass • Set 0x843E[6] to 1 to activate the Auto mode • Wait for at least one vertical period or vertical sync pulse to pass • Unblank video This Sequence must be done by the microcontroller at sys- tem power up, as well as each time there is a horizontal line rate change from the video source, for the PLL Auto mode to function properly. Pin Descriptions and Application Information Pin No. Pin Name Schematic Description 1 V Flyback Required for OSD synchronization and is also used for vertical blanking of the video outputs. The actual switching threshold is about 35% of V CC. For logic level inputs C4 can be a jumper, but for flyback inputs, an AC coupled differentiator is recommended, where R V is large enough to prevent the voltage at pin 1 from exceeding V CC or going below GND. C4 should be small enough to flatten the vertical rate ramp at pin 1. C 24 may be needed to reduce noise. 2V REF Bypass Provides filtering for the internal voltage which sets the internal bias current in conjunction with R EXT. A minimum of 0.1 µF is recommended for proper filtering. This capacitor should be placed as close to pin 2 and the pin 4 ground return as possible. www.national.com 10 |
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