Motore di ricerca datesheet componenti elettronici
  Italian  ▼
ALLDATASHEETIT.COM

X  

M41ST95YMX6F Scheda tecnica(PDF) 9 Page - STMicroelectronics

Il numero della parte M41ST95YMX6F
Spiegazioni elettronici  5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor
Download  35 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Produttore elettronici  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M41ST95YMX6F Scheda tecnica(HTML) 9 Page - STMicroelectronics

Back Button M41ST95YMX6F Datasheet HTML 5Page - STMicroelectronics M41ST95YMX6F Datasheet HTML 6Page - STMicroelectronics M41ST95YMX6F Datasheet HTML 7Page - STMicroelectronics M41ST95YMX6F Datasheet HTML 8Page - STMicroelectronics M41ST95YMX6F Datasheet HTML 9Page - STMicroelectronics M41ST95YMX6F Datasheet HTML 10Page - STMicroelectronics M41ST95YMX6F Datasheet HTML 11Page - STMicroelectronics M41ST95YMX6F Datasheet HTML 12Page - STMicroelectronics M41ST95YMX6F Datasheet HTML 13Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 9 / 35 page
background image
9/35
M41ST95Y*, M41ST95W
OPERATION
The M41ST95Y/W clock operates as a slave de-
vice on the SPI serial bus. Each memory device is
accessed by a simple serial interface that is SPI
bus compatible. The bus signals are SCL, SDI and
SDO (see Table 1., page 5 and Figure 7., page 8).
The device is selected when the Chip Enable input
(E) is held low. All instructions, addresses and
data are shifted serially in and out of the chip. The
most significant bit is presented first, with the data
input (SDI) sampled on the first rising edge of the
clock (SCL) after the Chip Enable (E) goes low.
The 64 bytes contained in the device can then be
accessed sequentially in the following order:
1.
Tenths/Hundredths of a Second Register
2.
Seconds Register
3.
Minutes Register
4.
Century/Hours Register
5.
Day Register
6.
Date Register
7.
Month Register
8.
Year Register
9.
Control Register
10. Watchdog Register
11 - 16.Alarm Registers
17 - 19.Reserved
20.
Square Wave Register
21 - 64.User RAM
The M41ST95Y/W clock continually monitors VCC
for an out-of tolerance condition. Should VCC fall
below VPFD, the device terminates an access in
progress and resets the device address counter.
Inputs to the device will not be recognized at this
time to prevent erroneous data from being written
to the device from a an out-of-tolerance system.
When VCC falls below VSO, the device automati-
cally switches over to the battery and powers
down into an ultra low current mode of operation to
conserve battery life. As system power returns and
VCC rises above VSO, the battery is disconnected,
and the power supply is switched to external VCC.
Write protection continues until VCC reaches
VPFD (min) plus tREC (min). For more information
on Battery Storage Life refer to Application Note
AN1012.
SPI Bus Characteristics
The Serial Peripheral interface (SPI) bus is intend-
ed for synchronous communication between dif-
ferent ICs. It consists of four signal lines: Serial
Data Input (SDI), Serial Data Output (SDO), Serial
Clock (SCL) and a Chip Enable (E).
By definition a device that gives out a message is
called “transmitter,” the receiving device that gets
the message is called “receiver.” The device that
controls the message is called “master.” The de-
vices that are controlled by the master are called
“slaves.”
The E input is used to initiate and terminate a data
transfer. The SCL input is used to synchronize
data transfer between the master (micro) and the
slave (M41ST95Y/W) devices.
The SCL input, which is generated by the micro-
controller, is active only during address and data
transfer to any device on the SPI bus (see Figure
7., page 8).
The M41ST95Y/W can be driven by a microcon-
troller with its SPI peripheral running in either of
the two following modes:
(CPOL, CPHA) = ('0', '0') or
(CPOL, CPHA) = ('1', '1').
For these two modes, input data (SDI) is latched in
by the low-to-high transition of clock SCL, and out-
put data (SDO) is shifted out on the high-to-low
transition of SCL (see Table 2., page 10 and Fig-
ure 8., page 10).
There is one clock for each bit transferred. Ad-
dress and data bits are transferred in groups of
eight bits. Due to memory size the second most
significant address bit is a Don’t Care (address bit
6).


Codice articolo simile - M41ST95YMX6F

Produttore elettroniciIl numero della parteScheda tecnicaSpiegazioni elettronici
logo
STMicroelectronics
M41ST84W STMICROELECTRONICS-M41ST84W Datasheet
452Kb / 31P
   5.0 or 3.0V, 512 bit 64 x 8 SERIAL RTC with SUPERVISORY FUNCTIONS
M41ST84W STMICROELECTRONICS-M41ST84W Datasheet
481Kb / 29P
   3.0/3.3V I2C Serial RTC with Supervisory Functions
M41ST84W STMICROELECTRONICS-M41ST84W Datasheet
302Kb / 34P
   3.0/3.3 V I2C serial RTC with 44 bytes of NVRAM and supervisory functions
M41ST84WMH STMICROELECTRONICS-M41ST84WMH Datasheet
452Kb / 31P
   5.0 or 3.0V, 512 bit 64 x 8 SERIAL RTC with SUPERVISORY FUNCTIONS
M41ST84WMH1 STMICROELECTRONICS-M41ST84WMH1 Datasheet
452Kb / 31P
   5.0 or 3.0V, 512 bit 64 x 8 SERIAL RTC with SUPERVISORY FUNCTIONS
More results

Descrizione simile - M41ST95YMX6F

Produttore elettroniciIl numero della parteScheda tecnicaSpiegazioni elettronici
logo
STMicroelectronics
M41ST85Y STMICROELECTRONICS-M41ST85Y Datasheet
530Kb / 34P
   5.0 OR 3.0V, 512 bit 64 x 8 SERIAL RTC and NVRAM SUPERVISOR
M41ST84Y STMICROELECTRONICS-M41ST84Y Datasheet
452Kb / 31P
   5.0 or 3.0V, 512 bit 64 x 8 SERIAL RTC with SUPERVISORY FUNCTIONS
M41T94 STMICROELECTRONICS-M41T94 Datasheet
433Kb / 31P
   512 Bit 64 bit x8 SERIAL RTC SPI SRAM
M41ST87W STMICROELECTRONICS-M41ST87W Datasheet
733Kb / 42P
   5.0, 3.3, or 3.0V, 1280 bit (160 x8) Secure Serial RTC and NVRAM Supervisor with Tamper Detection
M41ST85W STMICROELECTRONICS-M41ST85W_07 Datasheet
369Kb / 41P
   3.0/3.3V I2C combination serial RTC, NVRAM supervisor and microprocessor supervisor
M41ST85W STMICROELECTRONICS-M41ST85W_06 Datasheet
606Kb / 34P
   3.0/3.3V I2C Combination Serial RTC, NVRAM Supervisor and Microprocessor Supervisor
logo
Renesas Technology Corp
X5043 RENESAS-X5043 Datasheet
844Kb / 21P
   4K, 512 x 8 Bit CPU Supervisor with 4K SPI EEPROM
logo
STMicroelectronics
M41ST85W STMICROELECTRONICS-M41ST85W_11 Datasheet
450Kb / 43P
   3.0/3.3 V I2C combination serial RTC, NVRAM supervisor and microprocessor supervisor
logo
Cypress Semiconductor
CY14B512Q1 CYPRESS-CY14B512Q1_13 Datasheet
1Mb / 27P
   512-Kbit (64 K x 8) Serial (SPI) nvSRAM
logo
Renesas Technology Corp
R1LV0408C-C RENESAS-R1LV0408C-C Datasheet
97Kb / 14P
   4M SRAM (512-kword X 8-bit)
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35


Scheda tecnica Scarica

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEETIT.COM
Lei ha avuto il aiuto da alldatasheet?  [ DONATE ] 

Di alldatasheet   |   Richest di pubblicita   |   contatti   |   Privacy Policy   |   scambio Link   |   Ricerca produttore
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com