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FAN3223 Scheda tecnica(PDF) 21 Page - ON Semiconductor |
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FAN3223 Scheda tecnica(HTML) 21 Page - ON Semiconductor |
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21 / 29 page  www.onsemi.com 21 Applications Information Input Thresholds Each member of the FA N322x driver family consists of tw o identical channels that may be used independently at rated current or connected in parallel to double the individual current capacity. In the FA N3223 and FA N3224, channels A and B can be enabled or disabled independently using ENA or ENB, respectively. The EN pin has TTL thresholds for parts w ith either CMOS or TTL input thresholds. If ENA and ENB are not connected, an internal pull-up resistor enables the dr iver channels by default. ENA and ENB have TTL thresholds in parts w ith either TTL or CMOS INx threshold. If the channel A and channel B inputs and outputs are connected in parallel to increase the driver current capacity, ENA and ENB should be connected and driven together. The FA N322x family offers versions in either TTL or CMOS input thresholds. In the FA N322x T, the input thresholds meet industry-standard TTL-logic thresholds independent of the VDD voltage, and there is a hysteresis voltage of approximately 0.4 V. These levels per mit the inputs to be driven from a range of input logic signal levels for w hich a voltage over 2 V is considered logic HIGH. The driving signal for the TTL inputs should have fast rising and falling edges w ith a slew rate of 6 V/µs or faster, so a r ise time from 0 to 3.3 V should be 550 ns or less. With reduced slew rate, circuit noise could cause the driver input voltage to exceed the hysteresis voltage and retrigger the dr iver input, causing erratic operation. In the FA N322x C, the logic input thresholds are dependent on the VDD level and, w ith VDD of 12V, the logic rising edge threshold is approximately 55% of VDD and the input falling edge threshold is approximately 38% of VDD. The CMOS input configuration offers a hysteresis voltage of approximately 17% of VDD. The CMOS inputs can be used w ith relatively s low edges (approaching DC) if good decoupling and bypass techniques are incorporated in the system design to prevent noise from violating the input voltage hysteresis w indow . This allow s setting precise timing intervals by fitting an R- C c ircuit betw een the controlling signal and the IN pin of the dr iver. The s low rising edge at the IN pin of the driver introduces a delay betw een the controlling signal and the OUT pin of the driver. Static Supply Current In the IDD (static) typical performance characteristics (Figure 12 - Figure 14 and Figure 19 - Figure 21), the curve is produced w ith all inputs/enables floating (OUT is low ) and indicates the low est static IDD current for the tested configuration. For other states, additional current flow s through the 100 k Ω resistors on the inputs and outputs show n in the block diagram of each part (see Figure 5 - Figure 7). In these cases, the actual static IDD current is the value obtained from the curves plus this additional current. M illerDrive™ Gate Drive Technology FA N322x gate drivers incorporate the Miller Drive™ architecture show n in Figure 48. For the output stage, a combination of bipolar and MOS devices provide large currents over a w ide range of supply voltage and temperature variations. The bipolar devices carry the bulk of the current as OUT sw ings betw een 1/3 to 2/3 VDD and the MOS dev ices pull the output to the HIGH or LOW rail. The purpose of the Miller Drive™ architecture is to speed up sw itching by providing high current during the Miller plateau region w hen the gate-drain capacitance of the MOSFET is being charged or discharged as part of the turn-on / turn-off process. For applications that have zero voltage sw itching during the MOSFET turn-on or turn-off interval, the driver supplies high peak current for fast sw itching even though the Miller plateau is not present. This situation often occurs in synchronous rectifier applications because the body diode is generally conducting before the MOSFET is sw itched ON. The output pin slew rate is determined by VDD voltage and the load on the output. It is not user adjustable, but a series resistor can be added if a slow er rise or fall time at the MOSFET gate is needed. Input stage V DD V OUT Figure 48. MillerDrive™ Output Architecture Under-Voltage Lockout The FAN322x startup logic is optimized to drive ground- referenced N-channel MOSFETs w ith an under-voltage lockout ( UVLO) function to ensure that the IC starts up in an orderly fashion. When VDD is rising, yet below the UVLO level, this circuit holds the output LOW, regardless of the status of the input pins. After the part is active, the supply voltage must drop 0.2 V before the part shuts dow n. This hysteresis helps prevent chatter w hen low VDD supply voltages have noise from the pow er sw itching. This configuration is not suitable for driving high-side P-channel MOSFETs because the low output voltage of the driver w ould turn the P-channel MOSFET ON w ith VDD below the UVLO level. |
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Descrizione simile - FAN3223 |
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