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GS1510-CQR Scheda tecnica(PDF) 6 Page - Gennum Corporation

Il numero della parte GS1510-CQR
Spiegazioni elettronici  HDTV Serial Digital Deformatter
Download  11 Pages
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Produttore elettronici  GENNUM [Gennum Corporation]
Homepage  http://www.gennum.com
Logo GENNUM - Gennum Corporation

GS1510-CQR Scheda tecnica(HTML) 6 Page - Gennum Corporation

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GENNUM CORPORATION
522 - 47 - 00
6
32
LINE_CRC_ERR_C
Synchronous
wrt PCLK_IN
Output
Status Signal Output. Indicates a difference in the calculated
versus embedded CRC in the CHROMA channel. When
LINE_CRC_ERR_C is high, it indicates that the GS1510 has
detected a difference between the line based CRCs it
calculates for the CHROMA channel and the line based CRCs
embedded within the CHROMA channel. When
LINE_CRC_ERR_C is low, the embedded and calculated CRCs
match. Refer to Fig. 6 for timing information of
LINE_CRC_ERR_C.
33
LINE_CRC_ERR_Y
Synchronous
wrt PCLK_IN
Output
Status Signal Output. Indicates a difference in the calculated
versus embedded CRC in the LUMA channel. When
LINE_CRC_ERR_Y is high, it indicates that the GS1510 has
detected a difference between the line based CRCs it
calculates for the LUMA channel and the line based CRCs
embedded within the LUMA channel. When LINE_CRC_ERR_Y
is low, the embedded and calculated CRCs match. Refer to
Fig. 6 for timing information of LINE_CRC_ERR_Y.
34
FIFO_L
Synchronous
wrt PCLK_IN
Output
Status Signal Output. Used to control an external FIFO(s).
FIFO_L is normally high, but is set low for the EAV or SAV word
depending on the state of F_E/S. Refer to Fig. 4 for timing
information of FIFO_L relative to LUMA (DATA_OUT[19:10])
and CHROMA (DATA_OUT[9:0]).
35
TN
TEST
Test Pin. Used for test purposes only. This pin must be
connected to VDD for normal operation
36
OEN
Non-
synchronous
Input
Control Signal Input. Used to enable the DATA_OUT[19:0]
output bus or set it to a high Z state. When OEN is low, the
LUMA (DATA_OUT[19:10]) and CHROMA (DATA_OUT [9:0])
busses are enabled. When OEN is high, these busses are in a
high Z state.
39, 40, 41, 42, 43,
44, 45, 48, 49, 52
DATA_OUT[9:0]
(CHROMA channel)
Synchronous
wrt PCLK_IN
Output
CHROMA Output Data Bus. DATA_OUT [9] is
CHROMA_OUT[9] which is the MSB of the CHROMA output
signal (pin 52). DATA_OUT [0] is CHROMA_OUT[0] which is
the LSB of the CHROMA output signal (pin 39).
53, 54, 55, 56, 57,
60, 61, 62, 63, 64
DATA_OUT[19:10]
(LUMA channel)
Synchronous
wrt PCLK_IN
Output
LUMA Output Data Bus. DATA_OUT [19] is LUMA_OUT[9]
which is the MSB of the LUMA output signal (pin 64).
DATA_OUT [10] is LUMA_OUT[0] which is the LSB of the
LUMA output signal (pin 53).
65
LN_ERR
Synchronous
wrt PCLK_IN
Output
Status Signal Output. Used to indicate a Line Number error or
a mismatch between the embedded line number and the
flywheel line number when the flywheel is enabled. When
LN_ERR is high, a line number error is detected or the internal
flywheel indicates mismatching line numbers. Refer to Fig. 3
for timing information of LN_ERR relative to LUMA
(DATA_OUT[19:10]) and CHROMA (DATA_OUT [9:0]) Since
LN_ERR depends on the sequence of line numbers, a line
number error will actually cause LN_ERR to go high for two
lines.
66
SAV_ERR
Synchronous
wrt PCLK_IN
Output
Status Signal Output. Indicates a TRS error or a mismatch
between the embedded TRS and the flywheel TRS when the
flywheel is enabled. This signal is set high when an error in the
SAV TRS is detected or when the internal flywheel indicates
there is a mismatching SAV TRS. Refer to Fig. 3 for timing
information of SAV_ERR relative to LUMA (DATA_OUT[19:10])
and CHROMA (DATA_OUT [9:0]).
PIN DESCRIPTIONS
NUMBER
SYMBOL
TIMING
TYPE
DESCRIPTION


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