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S29GL512N Scheda tecnica(PDF) 12 Page - Cypress Semiconductor |
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S29GL512N Scheda tecnica(HTML) 12 Page - Cypress Semiconductor |
12 / 92 page Document Number: 002-01522 Rev. *B Page 12 of 92 S29GL512N S29GL256N S29GL128N but the standby current is greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. Refer to DC Characteristics on page 65 for the standby current specification. 7.6 Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. Refer to DC Characteristics on page 65 for the automatic sleep mode current specification. 7.7 RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/ write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (ICC5). If RESET# is held at VIL but not within VSS±0.3 V, the standby current is greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. Refer to the AC Characteristics tables for RESET# parameters and to Figure 15.3 on page 70 for the timing diagram. |
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