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NCV59749 Scheda tecnica(PDF) 3 Page - ON Semiconductor |
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NCV59749 Scheda tecnica(HTML) 3 Page - ON Semiconductor |
3 / 10 page NCV59749 www.onsemi.com 3 Table 2. ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Input Voltage Range VIN −0.3 to +6 V Input Voltage Range VBIAS −0.3 to +6 V Enable Voltage Range VEN −0.3 to +6 V Power-Good Voltage Range VPG −0.3 to +6 V PG Sink Current IPG 0 to +1.5 mA SS Pin Voltage Range VSS −0.3 to +6 V Feedback Pin Voltage Range VFB −0.3 to +6 V Output Voltage Range VOUT −0.3 to (VIN + 0.3) ≤ 6 V Maximum Output Current IOUT Internally Limited Output Short Circuit Duration Indefinite Continuous Total Power Dissipation PD See Thermal Characteristics Table and Formula Maximum Junction Temperature TJMAX +125 °C Storage Junction Temperature Range TSTG −55 to +150 °C ESD Capability, Human Body Model (Note 2) ESDHBM 2000 V ESD Capability, Machine Model (Note 2) ESDMM 200 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC−Q100−002. ESD Machine Model tested per AEC−Q100−003. Latch-up Current Maximum Rating ≤150 mA per AEC−Q100−004. Table 3. THERMAL CHARACTERISTICS Rating Symbol Value Unit Thermal Characteristics, QFN20, 5x5, 0.65P package Thermal Resistance, Junction−to−Ambient (Note 5) RqJA 30.5 °C/W Thermal Resistance, Junction−to−Case (bottom) (Note 6) RqJC 4.1 °C/W 3. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 4. Thermal data are derived by thermal simulations based on methodology specified in the JEDEC JESD51 series standards. The following assumptions are used in the simulations: − This data was generated with only a single device at the center of a high−K (2s2p) board with 3 in x 3 in copper area which follows the − JEDEC51.7 guidelines. − The exposed pad is connected to the PCB ground layer through a 4x4 thermal via array. Vias are 0.3 mm diameter, plated. − Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage. 5. The junction−to−ambient thermal resistance under natural convection is obtained in a simulation on a high−K board, following the JEDEC51.7 guidelines with assumptions as above, in an environment described in JESD51−2a. 6. The junction−to−case (bottom) thermal resistance is obtained by simulating a cold plate test on the IC exposed pad. Test description can be found in the ANSI SEMI standard G30−88. Table 4. RECOMMENDED OPERATING CONDITIONS (Note 7) Rating Symbol Min Max Unit Input Voltage VIN VOUT + VDO 5.5 V Bias Voltage VBIAS 2.7 5.5 V Junction Temperature TJ −40 125 °C Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 7. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. |
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