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CY7C1663KV18 Scheda tecnica(PDF) 16 Page - Cypress Semiconductor

Il numero della parte CY7C1663KV18
Spiegazioni elettronici  144-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
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Produttore elettronici  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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Document Number: 001-44060 Rev. *O
Page 16 of 31
CY7C1663KV18/CY7C1665KV18
TAP AC Switching Characteristics
Over the Operating Range
Parameter [19, 20]
Description
Min
Max
Unit
tTCYC
TCK clock cycle time
50
ns
tTF
TCK clock frequency
20
MHz
tTH
TCK clock high
20
ns
tTL
TCK clock low
20
ns
Setup Times
tTMSS
TMS setup to TCK clock rise
5
ns
tTDIS
TDI setup to TCK clock rise
5
ns
tCS
Capture setup to TCK rise
5
ns
Hold Times
tTMSH
TMS hold after TCK clock rise
5
ns
tTDIH
TDI hold after clock rise
5
ns
tCH
Capture hold after clock rise
5
ns
Output Times
tTDOV
TCK clock low to TDO valid
10
ns
tTDOX
TCK clock low to TDO invalid
0
ns
Notes
19. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
20. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.


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