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CY7C1460KV25 Scheda tecnica(PDF) 21 Page - Cypress Semiconductor |
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CY7C1460KV25 Scheda tecnica(HTML) 21 Page - Cypress Semiconductor |
21 / 32 page Document Number: 001-66679 Rev. *J Page 21 of 32 CY7C1460KV25/CY7C1462KV25 CY7C1460KVE25/CY7C1462KVE25 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. User guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Ambient temperature with power applied ................................... –55 °C to +125 °C Supply voltage on VDD relative to GND .......–0.5 V to +3.6 V Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD DC to outputs in tristate ....................–0.5 V to VDDQ + 0.5 V DC input voltage ................................. –0.5 V to VDD + 0.5 V Current into outputs (LOW) ........................................ 20 mA Static discharge voltage (per MIL-STD-883, method 3015) ......................... > 2001 V Latch-up current ................................................... > 200 mA Operating Range Range Ambient Temperature VDD VDDQ Commercial 0 °C to +70 °C 2.5 V + 5% 2.5 V – 5% to VDD Industrial –40 °C to +85 °C Neutron Soft Error Immunity Parameter Description Test Conditions Typ Max* Unit LSBU (Device without ECC) Logical Single-Bit Upsets 25 °C <5 5 FIT/ Mb LSBU (Device with ECC) 0 0.01 FIT/ Mb LMBU (All Devices) Logical Multi-Bit Upsets 25 °C 0 0.01 FIT/ Mb SEL (All Devices) Single Event Latch up 85 °C 0 0.1 FIT/ Dev * No LMBU or SEL events occurred during testing; this column represents a statistical 2, 95% confidence limit calculation. For more details refer to Application Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates”. Electrical Characteristics Over the Operating Range Parameter [16, 17] Description Test Conditions Min Max Unit VDD Power supply voltage – 2.375 2.625 V VDDQ I/O supply voltage for 2.5 V I/O 2.375 VDD V VOH Output HIGH voltage for 2.5 V I/O, IOH =1.0 mA 2.0 – V VOL Output LOW voltage for 2.5 V I/O, IOL =1.0 mA – 0.4 V VIH Input HIGH voltage [16] for 2.5 V I/O 1.7 VDD + 0.3 V V VIL Input LOW voltage [16] for 2.5 V I/O –0.3 0.7 V IX Input leakage current except ZZ and MODE GND VI VDDQ –5 5 A Input current of MODE Input = VSS –30 – A Input = VDD –5 A Input current of ZZ Input = VSS –5 – A Input = VDD –30 A IOZ Output leakage current GND VI VDDQ, output disabled -5 5 A Notes 16. Overshoot: VIH(AC) < VDD +1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2). 17. TPower-up: Assumes a linear ramp from 0 V to VDD (min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. |
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