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CY2XP21 Scheda tecnica(PDF) 7 Page - Cypress Semiconductor

Il numero della parte CY2XP21
Spiegazioni elettronici  125 MHz LVPECL Clock Generator
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Produttore elettronici  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY2XP21 Scheda tecnica(HTML) 7 Page - Cypress Semiconductor

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Document #: 001-52849 Rev. *B
Revised September 22, 2009
Page 7 of 7
All products and company names mentioned in this document may be the trademarks of their respective holders.
PRELIMINARY
CY2XP21
© Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC
psoc.cypress.com
Clocks & Buffers
clocks.cypress.com
Wireless
wireless.cypress.com
Memories
memory.cypress.com
Image Sensors
image.cypress.com
Document History Page
Document Title: CY2XP21 125 MHz LVPECL Clock Generator
Document Number: 001-52849
REV.
ECN NO.
Submission
Date
Orig. of
Change
Description of Change
**
2700242
04/30/09
KVM/PYRS New data sheet
*A
2718898
06/15/09
WWZ
Minor ECN to post data sheet to external web
*B
2767298
09/22/09
KVM
Add IDD spec for unterminated outputs
Change parameter name for IDD (terminated outputs) from IDD to IDDT
Remove IDD footnote about externally dissipated current
Add footnote reference to CINX:not 100% tested
Add max limit for TR, TF: 1.0 ns
Change TLOCK max from 10 ms to 5 ms
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