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TS68332VA20 Scheda tecnica(PDF) 5 Page - ATMEL Corporation |
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TS68332VA20 Scheda tecnica(HTML) 5 Page - ATMEL Corporation |
5 / 56 page 5 TS68332 2118A–HIREL–03/02 Development Serial In, Out, Clock DSI, DSO, DSCLK Serial I/O and clock for background debug mode TPU Channels TP15 - TP0 TPU channel input/output Serial I/O and clock for background debug mode TPU Clock In T2CLK External clock source to the TPU SCI Receive Data RXD Serial input to the SCI SCI Transmit Data TXD Serial output from the SCI Peripheral Chip Select PCS3 - PCS0 QSPI peripheral chip selects Slave Select SS Places the QSPI in slave mode QSPI Serial Clock SCK Furnishes the clock from the QSPI in master mode or to the QSPI in slave mode Master-in Slave-out MISO Furnishes serial input to the QSPI in master mode, and serial output from the QSPI in slave mode Master-out Slave-in MOSI Furnishes serial output from the QSPI in master mode, and serial input to the QSPI in slave mode Standby RAM V STBY Power supply for RAM Synchronizer Power V DDSYN Power supply to VCO System Power Supply and Return V DD, VSS Power supply and return to the MCU Table 1. Signal Index (Continued) Signal Name Mnemonic Function |
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Descrizione simile - TS68332VA20 |
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