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SLG46534 Scheda tecnica(PDF) 59 Page - Dialog Semiconductor |
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SLG46534 Scheda tecnica(HTML) 59 Page - Dialog Semiconductor |
59 / 172 page SLG46534_DS_107 Page 58 of 171 SLG46534 9.3.2 3-Bit LUT or D Flip Flop Macrocells Used as D Flip Flop Register Settings Table 49. DFF3 Register Settings Signal Function Register Bit Address Register Definition LUT3_0 or DFF3 Select reg<1187> 0: LUT3_0 1: DFF3 DFF3 Initial Polarity Select reg<1220> 0: Low 1: High DFF3 nRST/nSET Select reg<1221> 1: nSET from matrix out 0: nRST from matrix out DFF3 Output Select reg<1222> 0: Q output 1: nQ output DFF3 or Latch Select reg<1223> 0: DFF function 1: Latch function Table 50. DFF4 Register Settings Signal Function Register Bit Address Register Definition LUT3_1 or DFF4 Select reg<1186> 0: LUT3_1 1: DFF4 DFF4 Initial Polarity Select reg<1128> 0: Low 1: High DFF4 nRST/nSET Select reg<1129> 1: nSET from matrix out 0: nRST from matrix out DFF4 Output Select reg<1130> 0: Q output 1: nQ output DFF4 or Latch Select reg<1131> 0: DFF function 1: Latch function |
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