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SLG46533 Scheda tecnica(PDF) 81 Page - Dialog Semiconductor |
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SLG46533 Scheda tecnica(HTML) 81 Page - Dialog Semiconductor |
81 / 185 page SLG46533_DS_114 Page 80 of 184 SLG46533 Table 84. CNT/DLY6 Register Settings Signal Function Register Bit Address Register Definition LUT3_9 or Counter5 Select reg<1194> 0: LUT3_9 1: Counter6 Delay6 Mode Select or asynchronous counter reset reg<1305:1304> 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on either falling or rising edges / counter high level reset Counter/delay6 Clock Source Select reg<1308:1306> 000: Internal OSC clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: 25 MHz OSC clock 110: External Clock 111: Counter5 Overflow Counter/delay6 Output Selection for Counter mode reg<1309> 0: Default Output 1: Edge Detector Output Counter/delay6 Mode Selection reg<1311:1310> 00: Delay mode 01: One Shot 10: Freq. Detect 11: Counter mode Counter/delay6 Control Data reg<1575:1568> 1 – 255 |
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