Motore di ricerca datesheet componenti elettronici |
|
MRF89XA Scheda tecnica(PDF) 73 Page - Microchip Technology |
|
MRF89XA Scheda tecnica(HTML) 73 Page - Microchip Technology |
73 / 140 page 2010-2017 Microchip Technology Inc. Preliminary DS70000622D-page 73 MRF89XA 3.8 Data Processing 3.8.1 DATA PROCESSING BLOCK The MRF89XA data processing blocks are as illustrated in the Figure 3-16. The role of the data processing block is to interface the data to/from the modulator/demodulator and the host microcontroller access points (SPI, Interrupts (IRQ0 and IRQ1), DATA pins). It also controls all the configuration registers. The circuit contains several control blocks, which are described in the following paragraphs. The MRF89XA implements several data operation modes, each with their own data path through the data processing section. Depending on the data operation mode selected, some control blocks are active while others remain disabled. 3.8.2 DATA OPERATION MODES The MRF89XA has three different data operation modes that can be selected by the user or programmer: • Continuous mode: Each bit transmitted or received is accessed in real time at the DATA pin. This mode may be used if adequate external sig- nal processing is available. • Buffered mode: Each byte transmitted or received is stored in a FIFO and accessed through the SPI bus. The host microcontroller processing over- head reduced significantly compared to Continu- ous mode operation. The packet length is unlimited. • Packet mode (recommended): User only pro- vides/retrieves payload bytes to/from the FIFO. The packet is automatically built with preamble, Sync Word, and optional CRC, DC-free encoding, and the reverse operation is performed in recep- tion. The host microcontroller processing over- head is further reduced compared to Buffered mode. The maximum payload length is limited to the maximum FIFO limit of 64 bytes. FIGURE 3-16: MRF89XA DATA PROCESSING BLOCK DIAGRAM TABLE 3-4: DATA OPERATION MODE SELECTION Data Operation Mode DMODE1 DMODE0 Register Continuous 00 FTXRXIREG Buffered 01 FTXRXIREG Packet 1x FTXRXIREG Control DATA CONFIG SPI Packet Handler SYNC Recognition DATA IRQ0 IRQ1 SDO SDI SCK CSDAT RX TX TX/RX Data MRF89XA FIFO (+SR) |
Codice articolo simile - MRF89XA |
|
Descrizione simile - MRF89XA |
|
|
Link URL |
Privacy Policy |
ALLDATASHEETIT.COM |
Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |