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MRF89XA Scheda tecnica(PDF) 23 Page - Microchip Technology

Il numero della parte MRF89XA
Spiegazioni elettronici  Ultra Low-Power, Integrated ISM BandSub-GHz Transceiver
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Produttore elettronici  MICROCHIP [Microchip Technology]
Homepage  http://www.microchip.com
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MRF89XA Scheda tecnica(HTML) 23 Page - Microchip Technology

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 2010-2017 Microchip Technology Inc.
Preliminary
DS70000622D-page 23
MRF89XA
2.11
Serial Peripheral Interface (SPI)
The
MRF89XA
communicates
with
the
host
microcontroller through a 4-wire SPI port as a slave
device. An SPI-compatible serial interface allows the
user to select, command, and monitor the status of the
MRF89XA through the host microcontroller. All the
registers are addressed through the specific addresses
to control, configure, and read status bytes.
The SPI in the MRF89XA consists of the following two
sub-blocks, as illustrated in Figure 2-11:
• SPI CONFIG: This sub-block is used in all data
operation modes to read and write the configuration
registers which control all the parameters of the chip
(operating mode, frequency, and bit rate).
• SPI DATA: This sub-block is used in Buffered and
Packet mode to write and read data bytes to and
from the FIFO. (FIFO Interrupts can be used to
manage the FIFO content).
Both of these SPIs are configured in Slave mode while
the host microcontroller is configured as the master.
They have separate selection pins (CSCON and
CSDAT) but share the remaining pins:
• SCK (SPI Clock): Clock signal provided by the
host microcontroller
• SDI (SPI Input): Data Input signal provided by the
host microcontroller
• SDO (SPI Output): Data Output signal provided
by the MRF89XA
As listed in Table 2-5, only one interface can be
selected at a time, with CSCON having the priority:
TABLE 2-5:
CONFIG VS. DATA SPI
SELECTION
All the parameters can be programmed and set through
the SPI module. Any of these auxiliary functions can be
disabled when it is not required. After power-on, all
parameters are set to default values. The programmed
values are retained during Sleep mode. The interface
supports the read out of a status register, which pro-
vides detailed information about the status of the trans-
ceiver and the received data.
The MRF89XA supports SPI mode 0,0, which requires
the SCK to remain idle in a low state. The CS pins,
CSCON and CSDAT based on the mode (pin 14 and
15), must be held low to enable communication
between the host microcontroller and the MRF89XA.
The device’s timing specification details are listed in
Table 5-7. The SDO pin defaults to a high impedance
(hi-Z) state when any of the CS pins is high (the
MRF89XA is not selected). This pin has a tri-state
buffer and uses a bus hold logic.
As the device uses byte writes, any of the Chip Select
(CS) pins should be pulled low for 8 bits. Data bits on
the SDI pin (pin 17) are shifted into the device upon the
rising edge of the clock on the SCK pin (pin 18)
whenever the CS pins are low. The maximum clock
frequency for the SPI clock for CONFIG mode is 6
MHz. However, the maximum SPI Clock for DATA
mode (to read/write FIFO) is 1 MHz. Data is received by
the transceiver through the SDI pin and is clocked on
the rising edge of SCK. The MRF89XA sends the data
through the SDO pin and is clocked out on the falling
edge of SCK. The Most Significant bit (MSb) is sent first
in any data.
The SPI sequence diagrams are illustrated in
Figure 2-12 through Figure 2-15.
FIGURE 2-11:
SPI OVERVIEW AND HOST MICROCONTROLLER CONNECTIONS
CSDAT
CSCON
SPI
00
CONFIG
01
DATA
10
CONFIG
11
None
SPI
DATA
(Slave)
SDI
SDO
SCK
SPI
CONFIG
(Slave)
Config.
Registers
MRF89XA
CSDAT
PIC® Microcontroller
(Master)
CSCON
I/O
SDO
SDI
SCK
I/O
Configuration
Registers
FIFO


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